Review paper on Reversible Shift Register using Bidirectional Gate
Main Article Content
Abstract
This review paper examines the design and development of reversible shift registers using bidirectional gates, emphasizing their potential in low-power and energy-efficient digital systems. Reversible computing, a paradigm that ensures minimal energy dissipation by preserving information, has gained significant attention in recent years due to its applicability in emerging technologies such as quantum computing and energy-efficient VLSI design. Bidirectional gates play a critical role in implementing reversible shift registers by enabling efficient data flow in both left and right directions while maintaining reversibility. The paper reviews various architectures, including those based on quantum gates, CMOS transmission gates, and emerging reversible logic gates, to highlight the trade-offs in area, power, and delay. Design challenges, such as circuit complexity, gate count minimization, and fault tolerance, are discussed alongside solutions proposed in the literature. Furthermore, potential applications in data storage, signal processing, and future quantum computing systems are explored. The review concludes by identifying research gaps and outlining future directions for improving the scalability and practicality of reversible shift registers. This comprehensive analysis aims to serve as a valuable resource for researchers and practitioners in the field of reversible computing and digital design.
Article Details
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
References
Swathi Mummadi and Gnaneshwara Chary Udari, “An Efficient Reversible Universal Shift Register with Minimal Quantum Cost”, IEEE Women in Technology Conference (WINTECHCON), 2023.
B. Naresh Kumar Reddy, G. Sai Vishal Reddy and B. Veena Vani, “Design and Implementation of an Efficient LFSR using 2-PASCL and Reversible Logic Gates”, IEEE Bombay Section Signature Conference (IBSSC), IEEE 2020.
Sonam Gour and Gaurav Kumar Soni, “Reduction of Power and Delay in Shift Register using MTCMOS Technique”, Fourth International Conference on Trends in Electronics and Informatics, IEEE 2020.
S. Gupta and S. Kumar "A Novel Perspective in Designing a Low Quantum Cost Synchronous Reversible Counters" proc. IEEE Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) pp. 1-6 2020.
G. Prakash , Mehdi Darbandi , N. Gafar, Noor H. Jabarullah and Mohammad Reza Jalali “A New Design of 2-Bit Universal Shift Register Using Rotated Majority Gate Based on Quantum-Dot Cellular Automata T echnology” Springer International Journal of T heoretical Physics, PP-1-19, June 2019.
Partho Ghose and Md Naimur Rahman, “Design of Reversible Shift Registers Minimizing Number ofGates, Constant Inputs and Garbage Outputs”, International Conference on IEEE 2018.
P. Ghose M. N. Rahman M. M. Alam Polash and U. K. Acharjee "Design of Reversible Shift Registers Minimizing Number of Gates Constant Inputs and Garbage Outputs" proc. International Conference on Advances in Computing Communications and Informatics (ICACCI) pp. 752-758 2018.
Heranmoy Maity, Arindam Biswas, Anup Kr. Bhattacherjee and Anita Pal, “Design of quantum cost efficient 4-bit reversible universal shift register”, IEEE Conference Devices for Integrated Circuit (DevIC), IEEE 2017.
Shivshankar Mishra, Ram Racksha Tripathi and Devendra Kr. Tripathi, “Implementation of Configurable Linear Feedback Shift Register in VHDL”, International Conference on Emerging Trends in Electrical, Electronics and Sustainable Energy Systems, IEEE 2016.
Radhika Sharma and Balwinder Singh, “Design and Analysis of Linear Feedback Shift Register (LFSR) Using Gate Diffusion Input(GDI) Technique”, International Conference on Digital Circuit, IEEE 2016.
M. Soundharya and R. Arunkumar, "GDI based area delay power efficient carry select adder”, Online International Conference on Green Engineering and Technologies (IC-GET), Coimbatore, India, pp. 1-5, IEEE 2015.
Majumder P. L. Singh B. Chowdhury A. J. Mondal and V. Anand "Efficient design and analysis of N-bit reversible shift registers" proc. IEEE Int. conference on recent trends in computing pp. 199-208 2015.
Khushboo Sewak, Praveena Rajput and Amit Kumar Panda, “FPGA Implementation of 16 bit BBS and LFSR PN Sequence Generator: A Comparative Study”, Conference on Electrical, Electronics and Computer Science, IEEE 2014.
M. H. A. Khan "Design of reversible synchronous sequential circuits using pseudo Reed-Muller expressions" IEEE Transactions on Very Large Scale Integration (VLSI) Systems vol. 22 no. 11 pp. 2278-2286 2014.
Dr. R.V. Kshirsagar, Purushottam Y. Chawke: Design of 8 and 16 Bit LFSR with Maximum Length Feedback Polynomial & Its pipelined Structure Using Verilog HDL. International Journal on Recent and Innovation Trends in Computing and Communication, Vol. 2 issue 11, pp 3337- 3339, November 2014.