Teepu Sultan,Prof. Suresh S. Gawande. 2025. “VLSI Architecture for FIR Filter Using Radix-4 Booth Multiplier and CBL Adder”. International Journal of Advanced Research and Multidisciplinary Trends (IJARMT) 2 (1):390-402. https://www.ijarmt.com/index.php/j/article/view/110.