Low Power and Radiation Tolerance System on Chip (SoC) Architecture: A Review
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Abstract
The literature related to low-power and radiation-tolerant System-on-Chip design has expanded rapidly. The key problem pointed out by recent research is to continue to work reliably without the fault-tolerance systems introducing prohibitive power, area or time overhead. This review presents eighteen recent papers published in 2025 which are directly related to the development of low-power and radiation-tolerant SoC designs. The selected studies cover radiation characterisation and fault injection in FPGA and RISC-V systems; hardware redundancy and error-correcting techniques such as TMR, ECC, parity and scrubbing; low-power RISC-V and SoC techniques such as clock gating, power gating, architectural specialisation and energy-efficient acceleration; and circuit-level hardening of memories and logic cells. Across the research, a constant trade-off has been seen: higher dependability often means more hardware, storage, checking logic, or recovery activity, whereas low-power design strives to eliminate switching, wasteful computation, and idle resource utilisation.
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