VLSI Architecture for Discrete Hartley Transform using MCSLA based Partition Technique
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Abstract
A discrete Hartley transform (DHT) algorithm can be efficiently implemented on a highly modular and parallel architecture having a regular structure is consisting of multiplier and adder. Discrete Hartley Transform (DHT) is one of the transform used for converting data in time domain into frequency domain using only real values. We have proposed a new algorithm for calculating DHT of length 2N, where N=3 and 4. This project presents a high-performance VLSI architecture for computing the Discrete Hartley Transform (DHT), leveraging the Modified Carry Select Adder (MCSLA)-based partition technique. The DHT is widely used in signal and image processing due to its real-valued transformation, which reduces computational complexity compared to the Discrete Fourier Transform (DFT). To enhance speed and efficiency, we propose a novel architecture utilizing MCSLA for optimized arithmetic operations within the DHT. The design is synthesized using Verilog HDL and implemented on FPGA. Performance metrics such as area, delay, power consumption, and throughput are analyzed and compared with conventional DHT architectures. The proposed method shows significant improvements in speed and resource utilization, making it suitable for real-time signal processing applications.
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