VLSI Architecture for FIR Filter using Radix-4 Booth Multiplier and CBL Adder
Main Article Content
Abstract
The main objective of this research paper is to design architecture for finite impulse response (FIR) filter using radix-4 booth multiplier and common Boolean logic (CBL) adder. Finite Impulse response (FIR) filters are extensively utilized in digital signal processing in which different filter parts operate at different rates. It has applications in communication transmitters and receivers. FIR filters when implemented use multipliers and accumulators. There are various types of multiplier structure algorithms and their variations such as Combinational multiplier, Wallace Tree multiplier, Array multiplier and Sequential multiplier and Booth multiplier. Booth multipliers reduce the resulting number of partial products generated as a result of multiplication of two binary numbers. This paper presents a VLSI architecture for FIR filters integrating the Radix-4 Booth Multiplier and Carry Bypass Logic (CBL) Adder, improving speed, power efficiency, and area utilization. Performance comparisons with conventional architectures highlight the benefits of the proposed design.
Article Details
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
References
K. Sravani, M. Saisri, U. Vidya Sivani and A.Ramesh Kumar, “Design and Implementation of Optimized FIR Filter using CSA and Booth Multiplier for High Speed Signal Processing”, 4th International Conference for Emerging Technology (INCET), IEEE 2023.
A. S. Kumar et al., "An Efficient AVR interfaced Bluetooth controlled Robotic Car system," 2023 13th International Conference on Cloud Computing, Data Science & Engineering (Confluence), India, pp. 499-502, 2023.
A. S. Kumar et al., "A Novel RRAM-based FPGA architecture with Improved Performance and Optimization Parameters," 2022 IEEE 19th India Council International Conference (INDICON), Kochi, India, pp. 1-5, 2022.
B. N. K. Reddy and A. S. Kumar, "An Efficient Low-Power VIP based VC Router Architecture for Mesh-based NoC," 2022 IEEE 19th India Council International Conference (INDICON), India, pp. 1-5, 2022.
Raghava Rao, K., Naresh Kumar Reddy, B. & Kumar, A.S. “Using advanced distributed energy efficient clustering increasing the network lifetime in wireless sensor networks”, Soft Computing, 2023.
G. Shanthi, A. S. Kumar, et al., “An Efficient FPGA Implementation of Cascade Integrator Comb Filter,” 2022 International Conference on Intelligent Innovations in Engineering and Technology (ICIIET), pp. 151-156, 2022.
Sai Kumar, U. Siddhesh, N. Sai kiran and K. Bhavitha, “Design of High Speed 8-bit Vedic Multiplier using Brent Kung Adders,” 2022 13th International Conference on Computing Communication and Networking Technologies (ICCCNT), pp. 1-5, 2022.
Sayed, J. F., Hasan, B. H., Muntasir, B., Hasan, M., & Arifin, F. (2021). “Design and Evaluation of a FIR Filter Using Hybrid Adders and Vedic Multipliers”. 2021 2nd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST).
S. China Venkateshwarlu, Mohammad, Chandra Shaker Pittala and Rajeev Ratna Vallabhuni , “Optimized Design of Power Efficient FIR Filter Using Modified Booth Multiplier”, 4th International Conference on Recent Trends in Computer Science and Technology, IEEE 2021.
Ghasemi, Mir Majid, Amir Fathi, Morteza Mousazadeh, and Abdollah Khoei, “A new high speed and low power decoder/encoder for Radix‐4 Booth multiplier,” International Journal of Circuit Theory and Applications, 2021.
Chang, Yen-Jen, Yu-Cheng Cheng, Shao-Chi Liao, and Chun-Huo Hsiao, “A Low Power Radix-4 Booth Multiplier with Pre-Encoded Mechanism,” IEEE Access 8, 2020.
Akshitha V. Ramesh et al. "Implementation and Design of FIR Filters using Verilog HDL and FPGA" Perspectives in Communication Embedded-systems and Signal-processing-PiCES vol. 4.5 pp. 85-88, 2020.
Ranjeeta Yadav Rohit Tripathi and Sachin Yadav "FPGA Implementation of Efficient FIR Filter" International Journal of Engineering and Advanced Technology (IJEAT) vol. 9, no. 3 February 2020.
Zhang, Tingting, Weiqiang Liu, Jie Han, and Fabrizio Lombardi, “Design and Analysis of Majority Logic Based Approximate Radix-4 Booth Encoders,” In IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 1-6. IEEE, 2019.
Gharabaghlo, Nader Sharifi, and Tohid Moradi Khaneshan, “Performance Analysis of High Speed Radix-4 Booth Encoders in CMOS Technology,” Majlesi Journal of Electrical Engineering 13, no. 3, 49-57, 2019.
Madugula Sumalatha Panchala Venkata Naganjaneyulu and K. Satya Prasad "Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising" Microprocessors and Microsystems vol. 71 pp. 102883, 2019.
Oguzhan COSKUN and A. V. C. I. Kemal "FPGA Schematic Implementations and Comparison of FIR Digital Filter Structures" Balkan Journal of Electrical and Computer Engineering vol. 6.1 pp. 20-28, 2018.
D. Kalaiyarasi and M. Saraswathi, “Design of an Efficient High Speed Radix-4 Booth Multiplier for both Signed and Unsigned Numbers”, 4th International Conference on Advances in Electrical, Electronics, Information, Communication and Bio-Informatics (AEEICB), IEEE 2018.