Optimization Delay of Blowfish Symmetric-Key Block Cipher using Modified Carry Select Adder
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Abstract
The Blowfish symmetric-key block cipher is a widely used encryption algorithm known for its simplicity, flexibility, and strong security. However, in hardware-based cryptographic systems, speed and efficiency are critical factors, especially for real-time applications. This paper presents an optimized hardware implementation of the Blowfish cipher using a Modified Carry Select Adder (MCSA) to reduce computational delay during encryption and decryption processes. The Carry Select Adder, known for its high-speed performance, is further enhanced by integrating Binary to Excess-1 Converter (BEC) logic to minimize area and power consumption while maximizing speed. The Blowfish algorithm’s key scheduling and data processing modules, which involve intensive arithmetic operations, are redesigned using MCSA architecture. The proposed design is modeled in Verilog and synthesized using Xilinx FPGA tools. Comparative analysis is performed against traditional adder implementations in terms of delay, area utilization, and power efficiency. Simulation results demonstrate a significant reduction in propagation delay and improved throughput without compromising the security strength of the cipher. This optimization makes the Blowfish cipher more suitable for applications requiring high-speed and low-power encryption, such as embedded systems, wireless networks, and IoT devices. The proposed approach contributes to the development of efficient and secure hardware-based cryptographic solutions.
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