Digital Parallel FIR Filters using Different Multiplier and Adder: A Study
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Abstract
Finite Impulse Response (FIR) filters are essential components in digital signal processing (DSP) systems, offering inherent stability and linear phase characteristics. With growing demands for real-time, high-throughput signal processing, efficient hardware implementation of FIR filters has become increasingly critical. This study presents a comparative analysis of Digital Parallel FIR Filter architectures using different types of multipliers and adders to optimize speed, area, and power consumption. Various multipliers, such as Booth Multiplier, Wallace Tree Multiplier, and Array Multiplier, are examined in conjunction with fast adder circuits including Carry Look-Ahead Adder (CLA), Carry Select Adder (CSLA), and Common Boolean Logic (CBL) Adders. The proposed design methodology emphasizes parallel processing to enhance computational efficiency. Simulation results using hardware description languages (VHDL/Verilog) and synthesis on FPGA platforms demonstrate that certain combinations, such as the Booth Multiplier with CSLA, offer notable improvements in execution time and power efficiency. This study aims to guide VLSI designers in selecting optimal arithmetic units for FIR filter implementation based on application-specific constraints and performance requirements.
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